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r s tel-2060c/cr ! s tel-2060c/cr

STEL-2060C 2 functional description convolutional encoding and viterbi decoding are used to provide forward error correction (fec) which improves digital communication performance over a noisy link. the STEL-2060C is a specialized product designed to perform this specific communications related function. at the encoder a stream of symbols is created which introduces a high degree of redundancy. this enables accurate decoding of the information despite a high symbol error rate resulting from an impaired communications link. the STEL-2060C contains a k = 7 viterbi decoder. the data inputs can be in offset binary or offset signed-magnitude formats, with 3-bit soft decision. auto node sync is provided for applications where symbol uncertainty can occur. rate 2 / 3 , 3 / 4 , 4 / 5 , 5 / 6 , 6 / 7 and 7 / 8 punctured signals can be decoded, as well as non-punctured, rate 1 / 2 , signals. the polynomials and puncturing patterns used are industry standards. depuncturing logic is incorporated into the decoder to provide automatic depuncturing of received data at rates 2 / 3 , 3 / 4 and 7 / 8 when the puncturing patterns supported by the device are used. a ber monitor is also provided in the device, along with a circuit for computing the mean value of the ber over an extended period. these circuits operate with punctured codes as well as unpunctured. the STEL-2060C incorporates a descrambler for signals scrambled with the invert g2 algorithm. (with this method the g2 symbols are logically inverted at the encoder. this provides a very effective level of scrambling for the purpose of avoiding long strings of ones or zeroes in the transmitted signal using bpsk modulation.) features n 45 mbps operating rate n constraint length k = 7 g 1 = 171 8 g 2 = 133 8 n multiple rates: rate 1 / 2 as well as punctured codes at rates 2 / 3 through 7 / 8 n internal depuncturing capability at rates 2 / 3 , 3 / 4 and 7 / 8 n multiple devices can be multiplexed to give higher data rates n optimized interface to operate with bpsk and qpsk demodulators n auto node sync capability n differential decoder n invert g2 descrambler n internal ber monitor and ber measurement circuit n 5.2 db coding gain @10 -5 ber (r = 1 / 2 ) n 100-pin pqfp package n 0.5 micron cmos technology block diagram symbol alignment and depuncturing circuit branch metric assignment viterbi decoder (acs) traceback memory timing and control g1 g2 pncg1/g2 dclkin differential decoder dato auto sync ber monitor and counter berr symckin g1err g2err oos odclk ddif reset ldg2 parl obin addr int 3 8 2 3 3 data node sync control to all registers ? interface rd csel wr rate extsel 3 dscram count 8 thres h 8
3 STEL-2060C package: 100-pin hqfp thermal coefficient, q ja = 30 c/w pin configuration notes: (1) tolerances on pin spacing are not cumulative (2) dimensions shown are at seating plane (3) i.c. denotes internal connection. this pin must be left unconnected. do not use for vias. (4) n.c. denotes no connection. these pins can be used for vias. 21 v ss 22 n.c. 23 pncg1 24 pncg2 25 dscram 26 sync 27 ldg2 28 n.c. 29 n.c. 30 v dd 31 v dd 32 count 0 33 count 1 34 count 2 35 count 3 36 count 4 37 count 5 38 count 6 39 count 7 40 v dd 41 v ss 42 v dd 43 parl 44 read 45 v ss 46 addr 2 47 addr 1 48 addr 0 49 write 50 csel 51 v dd 52 v dd 53 n.c. 54 data 7 55 data 6 56 data 5 57 data 4 58 data 3 59 data 2 60 data 1 61 data 0 62 n.c. 63 int 64 n.c. 65 v ss 66 odclk 67 n.c. 68 v ss 69 dato 70 n.c. 71 oos 72 auto 73 n.c. 74 i.c. 75 n.c. 76 berr 77 g1err 78 g2err 79 v dd 80 v dd 81 thr 0 82 thr 1 83 thr 2 84 thr 3 85 thr 4 86 thr 5 87 thr 6 88 thr 7 89 extsel 90 v ss 91 v ss 92 v ss 93 v dd 94 v ss 95 ddif 96 v ss 97 rate 2 98 rate 1 99 rate 0 100 v dd pin connections 1v dd 2 n.c. 3 n.c. 4g1 0 5g1 1 6g1 2 7g2 0 8g2 1 9g2 2 10 n.c. 11 obin 12 n.c. 13 v ss 14 symckin 15 n.c. 16 v ss 17 dclkin 18 n.c. 19 v ss 20 reset top view 0.941" 0.010" 0.742" 0.005" 0.487" 0.003" 0.705" 0.010" 0.11" nom. 0.122" max. 0.014" 0.002" 0.0256" 0.002" 0.031" 0.005" 0.009" 0.005" pin 1 identifier 1 80 50 30 81 51 31 100 detail of pins
STEL-2060C 4 input signals reset reset . a logic low on this asynchronous input will completely reset all registers in the decoder to an initial condition within 20 nsec. normal operation will commence after reset goes high. this will not affect the values stored in the decision path memory but will reset the node sync state to the initial condition. dclkin d ecoder cl oc k in put. it is the reference clock for all internal synchronous functions in the decoder when operating in the internal puncturing mode. it should nominally be a square wave with a maximum frequency of 45 mhz, corresponding to a decoded data rate of 45 mbps. when operating at rate 1 / 2 and in the external puncturing mode this clock will be generated internally from symckin , and dclkin should be connected to ground. symckin sym bol c loc k in put. this is the reference clock for all internal synchronous functions in the symbol alignment and depuncturing circuits. it should nominally be a square wave with a maximum frequency of 90 mhz. its frequency should be equal to f dclkin /2r in the parallel input mode ( parl = 1) and equal to f dclkin /r in the sequential input mode ( parl = 0), where r is the decoding rate when using internal depuncturing. please refer to the section on punctured mode operation for more detailed information. g1 2-0 , g2 2-0 the g1 2-0 and g2 2-0 signals are the 3-bit soft decision input symbols to the decoder. they are presented to the decoder either sequentially or in parallel depending on the states of the parl and rate 2-0 inputs. in the parallel mode ( parl = 1) the symbols are clocked into the device on the rising edges of symckin when rate 2-0 = 0 (rate 1 / 2 and external depuncturing) and on both edges of symckin when rate 2-0 1 0 (internal depuncturing). in the sequential mode ( parl = 0) in which the g2 2-0 inputs are not used, both the g1 and g2 symbols are loaded via the g1 2-0 pins. the g1 symbols are then latched in on the rising edges of symckin when ldg2 is low and the g2 symbols are latched in on the rising edges of symckin when ldg2 is high. ldg2 when this signal is high during a rising edge of symckin the symbol loaded into the g1 2-0 pins will be g2. this function is only active when parl is set low (sequential input mode) and rate 2-0 is set to 000 (rate 1 / 2 operation or external puncturing mode). if auto node sync is used, the ldg2 signal can be derived by dividing the symckin signal by two. the auto node sync will then compensate for the phase ambiguity. parl when this signal is high, the input symbols are accepted in par alle l by the chip, using the g1 2-0 pins for the g1 symbols and the g2 2-0 pins for the g2 symbols. when it is set low, the inputs are accepted sequentially, using the g1 2-0 pins for both symbols. the sequential input is most suited for bpsk data, and the parallel input is most suited for qpsk data. the auto node sync sequence will operate on the assumption that the signal is bpsk modulated when parl is set low and qpsk modulated when it is set high. setting parl low adds two cycles of odclk to the pipeline delay. obin the STEL-2060Ccc can accept the soft-decision input data in either o ffset bin ary or offset signed-magnitude formats. when the obin input is set high, the format expected will be offset binary; when it is set low it will be offset signed- magnitude. the meanings of the 3-bit values for these two codes is shown in the following table: obin = 1 obin = 0 value 111 111 most confident + 110 110 (data = 1) 101 101 100 100 least confident + 011 000 least confident C 010 001 001 010 (data = 0) 000 011 most confident C when using the STEL-2060Ccc with hard-decision data, the symbols should be loaded into the g1 2 and g2 2 pins. the other symbol inputs should be set to a logic high level and obin should be set low. rate 2-0 these signals select the decoding rate for unpunctured operation (rate 1 / 2 ) and internally supported depuncturing patterns (rates 2 / 3 , 3 / 4 and 7 / 8 ). these patterns are shown in the following table, where a 0 in the pattern indicates a punctured symbol: rate 2-0 rate pattern 000 1 / 2 n.a. 001 2 / 3 g1: 10 g2: 11 100 3 / 4 g1: 101 g2: 110 010 7 / 8 g1: 1000101 g2: 1111010 other puncturing patterns can be implemented externally using the pncg1 and pncg2 inputs. ddif when this input is set high, it causes the data out of the viterbi d ecoder to be dif ferentially decoded. this adds one cycle of odclk to the pipeline delay.
5 STEL-2060C dscram when this input is set high, it causes the g2 symbols to be inverted before they enter the viterbi decoder, thereby reversing the effect of the g2 inversion if an "invert g2" scrambler is implemented at the encoder. pncg1, pncg2 the pncg1 and pncg2 signals are used to control the STEL-2060Ccc when operating in punctured modes not supported by the internal puncturing logic. in normal operation (rate 1 / 2 and when using internal puncturing) these pins should be set low. in the external depuncturing mode, the pncg1 signal must be set high to indicate that the g1 symbol is punctured and the pncg2 signal must be set high to indicate that the g2 symbol is punctured. a symbol will be depunctured when the pncg1 or pncg2 signals are high during the rising edge of symckin which latches the corresponding symbol in to the decoder. rate 2-0 should be set to 000 when operating in external depuncturing mode. zero value metrics will be substituted internally for the actual metrics corresponding to the signals present on the g1 2-0 and g2 2-0 pins at that time. internal depuncturing can be selected by the use of the rate inputs. sync when the sync input is set high during the rising edge of symckin the internal symbol synchronization will be changed. when auto node sync is not desired this pin should be set low. it should be connected to the auto output to use the auto node sync capability of the STEL-2060Ccc. the state of this circuit will always be set to normal after a reset. count 7-0 the 8-bit count 7-0 input defines the period (number of bits) used in the node synchronization circuit when extsel is set high. the 8-bit number n is used to set up a period of (256n + 256) bits internally, where n is the value of count 7-0 . an out-of-sync condition is declared (i.e., the output pin oos is set high and auto pulses high) if the renormalization count exceeds the threshold value during a period of this number of bits. thr 7-0 the 8-bit thr 7-0 input defines the threshold for node synchronization when extsel is set high. the 8-bit number n is used to set up a threshold value of (8n + 6) internally, where n is the value of thr 7-0 . an out-of-sync condition is declared (i.e., the output pin oos is set high and auto pulses high) if the renormalization count exceeds this threshold value. extsel when the extsel input is set high, the count 7-0 and thr 7-0 information is derived from the count 7-0 and thr 7-0 input pins. when it is set low, this information is derived from the data written into addresses 0 and 1. output signals odclk o utput d ata cl oc k . all outputs change on the rising edge of this clock. the falling edge of odclk can be used as a strobe for dato output, which is guaranteed to be valid on this edge. dato decoded dat a o utput. this is the output of the viterbi decoder. this signal changes on the rising edges of odclk . in rate 1 / 2 operation there will be a pipeline delay of 526 cycles of odclk from the g1 2-0 / g2 2-0 inputs to the dato output when ddif is set low and parl is set high. setting ddif high adds one cycle to this value and setting parl low adds two cycles. oos this output pin serves as a flag for the o ut- o f- s ync condition. when it goes high it signifies that the renormalization count in the internal node sync circuit has exceeded the threshold value set by the thr 7-0 signal, declaring an out-of-sync condition. it will remain high until this condition ceases to exist. i.e., until the next time the threshold is not exceeded during a complete count period. auto this is the feedback signal from the internal node sync correction circuit. it will pulse high for one cycle of dclkin each time the renormalization count in the internal node sync circuit has exceeded the threshold value set by the thr 7-0 signal and the out-of-sync condition is declared. it should be connected to the sync input when using the internal node sync facility. berr the b it err or output indicates that an error has been detected in either the g1 or g2 symbols corresponding to the current output bit. g1err the g1 err or output indicates that an error has been detected in the g1 symbol corresponding to the current output bit. g2err the g2 err or output indicates that an error has been detected in the g2 symbol corresponding to the current output bit. note : the berr , g1err and g2err signals are in nrz format, i.e., the signals will not return to zero between two consecutive errors. to generate pulsed outputs, the signals can be gated with the odclk signal. microprocessor interface data 7-0 all i/o and control functions can be accessed via the data 7-0 bus with the associated control signals. the STEL-2060Ccc is used as a memory or i/o mapped peripheral to the host processor.
STEL-2060C 6 addr 2-0 the 3-bit address bus is used to access the various i/o functions, as shown in the memory map table, below. note that some addresses contain both read and write registers. these read and write mode registers are separate and contain different data. write the write input is used to write data to the microprocessor data bus. it is active low and is normally connected to the write line of the host processor. read the read input is used to read data from the microprocessor data bus. it is active low and is normally connected to the read line of the host processor. csel the c hip sel ect input can be used to selectively enable the microprocessor data bus. it is active low. int the int errupt output indicates when the period counter in the ber monitor has completed a count period, and that a new value of berct is ready to be read from addresses 0 h and 1 h , when int will go high for one symbol period. input (write) functions count 7-0 the 8-bit count 7-0 data defines the period (i.e., the number of bits) used in the node synchronization circuit. the 8-bit number n is used to set up a period of (256n + 256) internally, where n is the value of count 7-0 . if the renormalization count exceeds the threshold value during a period of this number of bits then an out-of-sync condition is declared (i.e., the output pin oos is set high and auto pulses high). reset value 00 h . thr 7-0 the 8-bit thr 7-0 data defines the threshold for node synchronization when extsel is set low. the function is identical to that of the thr 7-0 input signal. reset value 00 h . bper 23-0 the 24-bit b er per iod data is used to set the period (number of data bits) over which the mean ber is measured by the ber monitor. the period used is 1000 times the value of bper 23-0 . reset value ffffff h . note: the ber count function incorporated in the STEL-2060Ccc uses a counter to count the number of thousands of bits received. when the value of this counter is equal to the value written into bper 23-0 the number of errors counted is dumped into the berct 15-0 output register and can be read from read addresses 0-1 h . simultaneously, both the error and bit counters are reset and the process is restarted, and an interrupt (int) is generated to indicate that the new value is ready to be read. since the default (reset) value of the bper 23-0 register is ff ff ff h a potential problem occurs if the desired value is not written into this register before the value of the counter has already incremented past this value. if this is not done the equality will not be detected until after the counter overflows and increments to the desired value once again. even at the maximum rate of 45 mbps this will take over 6 minutes and, at a more modest data rate, such as 1 mbps, it will take over 4 1 / 2 hours! in any case, the user can easily be misled into believing that the circuit is not operating correctly since the interrupts will not be generated as expected. it is therefore imperative that the bper 23-0 value be written into the STEL-2060Ccc as soon as possible after a reset to ensure that this condition does not take place. the maximum time allowable is just less than the desired interrupt period itself, since the counter begins counting right after the reset is released. e.g., if the desired interrupt period is one second, the bper 23-0 value must be written within one second of the reset. at a data rate of 1 mbps the period would correspond to 10 6 bits and the correct bper 23-0 value would be 10 3 , or 00 03 e8 h . if, for some reason, it is not possible to do this, a dummy value should first be written into the STEL-2060Ccc. this should be large enough so that, at the time of writing, the bit counter will not have exceeded the dummy value. in this way the first interrupt will be generated within a reasonable period of time and the dummy value can then be overwritten with the desired value. again, care must be taken to ensure that the bper 23-0 value written is greater than the instantaneous counter value, otherwise the same problem will occur. e.g., in the above example, if it is not possible to write the bper 23-0 value until 5 seconds after the reset, then a dummy bper 23-0 value corresponding to >5 seconds, e.g., 6 seconds, or 00 17 70 h should first be written. the desired value of 00 03 e8 h must then be written within one second of an interrupt generated by the STEL-2060Ccc, thereby ensuring that the counter has not exceeded the new value at that time. output (read) functions berct 15-0 the 16-bit b it er ror c oun t data represents the mean bit error rate over the period determined by the ber period data bper 23-0 . the actual ber is given by: 8 x berct 15-0 ber = 1000 x bper 23-0 the value will be updated each time the period counter completes its count. completion is indicated by the int output going high for one clock cycle. if the accumulator overflows during a measurement period its output will be caused to saturate at a value of ffff h .
7 STEL-2060C microprocessor interface memory map write mode registers addr 2-0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0 count 7 count 6 count 5 count 4 count 3 count 2 count 1 count 0 1 thr 7 thr 6 thr 5 thr 4 thr 3 thr 2 thr 1 thr 0 2 3 bper 7 bper 6 bper 5 bper 4 bper 3 bper 2 bper 1 bper 0 4 bper 15 bper 14 bper 13 bper 12 bper 11 bper 10 bper 9 bper 8 5 bper 23 bper 22 bper 21 bper 20 bper 19 bper 18 bper 17 bper 16 read mode registers addr 2-0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0 berct 7 berct 6 berct 5 berct 4 berct 3 berct 2 berct 1 berct 0 1 berct 15 berct 14 berct 13 berct 12 berct 11 berct 10 berct 9 berct 8 punctured mode operation concept of puncturing in punctured codes some of the symbols generated by the convolutional encoder are deleted, or punctured, from the transmitted sequence. for example, in a rate 1 / 2 (unpunctured) sequence, four symbols are transmitted for every two data bits. if one symbol out of every group of four was punctured from the sequence then only three symbols would be transmitted for every two data bits. this would result in a rate 2 / 3 code. the coding gain is significantly less than that for unpunctured operation, but this is the trade-off for the reduced bandwidth required to transmit the information. the STEL-2060Cc decoder is designed to operate with punctured codes as well as rate 1 / 2 code. two methods are provided for depuncturing the symbols. the external method can be used for all rates and patterns up to rate 7 / 8 by indicating which symbols were punctured at the encoder (and then reinserted prior to decoding) with the pncg1 and pncg2 signals. when one of these signals is set high the input data at the corresponding symbol input is ignored, and the internally generated metric for the symbol pair (g1 and g2) assigns a zero weight to the punctured symbol in the pair. this is done because the viterbi decoder has no way of knowing what the punctured symbol should have been. the recommended puncturing sequences for the various (n-1) / n rates of punctured operation are shown in the tables. the portions shown in boldface are the basic sequences, which are then repeated. the use of the pncg1 and pncg2 signals for rate 3 / 4 is shown in the external puncturing timing diagrams. the sequence for rate 3 / 4 is g1 g2 p g2 g1 p, and the punctured symbols are marked with asterisks in the timing diagrams. using internal depuncturing the internal depuncturing method supports rates 2 / 3 , 3 / 4 and 7 / 8 using the puncturing sequences specified in the tables, and the node sync process will automatically find the correct places to reinsert the punctured symbols. the puncturing sequences used for the rates supported are shown in the tables, along with the speeds of the two input clocks, symckin and dclkin . the portions shown in boldface are the basic sequences, which are then repeated. the symbol sequence for rate 2 / 3 is shown in the internal puncturing timing diagrams. the sequence is g1 g2 p g2; only g1 symbols are punctured in this particular sequence. the symckin and dclkin clocks are used to clock in the symbols and to clock out the data bits. the speeds of these two clocks vary according to the modes and rate in use. when operating in the external depuncturing modes the dclkin signal is not used and the symckin speed will be equal to the data rate (d) in the parallel mode ( parl = 1) and be equal to twice the data rate (2d) in the sequential mode ( parl = 0). in the internal depuncturing modes, however, dclkin is used and the speed of symckin will be as shown in the tables. the depuncturing circuit in the STEL-2060Cc takes symbols synchronized to the symckin signal and depunctures them, i.e., inserts dummy symbols into the signal stream at the appropriate positions. to do this the circuit handles the symbols as a group of up to four pairs, depending on the code rate. this circuit operates at the symckin rate and, at this point, the group of depunctured symbols is transferred into another set of registers clocked with dclkin. there is an internal timing requirement that the falling edge of dclkin
STEL-2060C 8 must follow the rising edge of symckin by a minimum of 8 nsec. at this instant, otherwise the handover will not occur correctly. this occurs once every 4 cycles of dclkin at rate 7 / 8 , every 2 cycles at rate 3 / 4 and every 3 cycles at rate 2 / 3 , the number of cycles of symckin depending on whether the parallel or sequential input mode is used, as well as the code rate. two examples of clock phasing for rate 3 / 4 parallel operation are shown below. here, the timing is such that the falling edges of dclkin only coincide with falling edges of symckin, never with rising edges. in this case the timing violation never occurs at any speed, since the non-coincident falling edges of dclkin will trail the rising edges of symckin by approximately 8 nsec. at a speed of 45 mbps. again, the same caveat regarding jitter must be observed. however, the symbol signal setup and hold requirements, shown in page 11 of the data sheet make it necessary for symckin to have a minimum low time of 12 nsec. to satisfy these requirements, so that it is not possible for this signal to be a square wave above 40 mhz for this reason. since the method for eliminating the clock timing violation presented here relies on the use of square waves (50% mark-space ratio), it cannot be used above 40 mhz because of the setup and hold time requirements. again, a similar condition exists for rate 7 / 8 operation, as shown below. symckin dclkin good bad in the first example the falling edges of dclkin never coincide with the rising edges of symckin. thus the timing violation will never occur provided that the delay from the non-coincident rising edges of symckin to the following falling edge of dclkin (shown by the arrows) exceeds 8 nsec. in the second case the falling edge of dclkin coincides with the rising edge of symckin once every two cycles of dclkin, resulting in a 50% probability that this may be the point at which the handover occurs, creating the problem discussed above. there are several ways to satisfy the timing requirement, depending on the code rate. one effective way which works at all rates is to generate symckin from dclkin by puncturing the clock to reduce its frequency while keeping all the edges synchronized; this will require the use of a small fifo to buffer the input symbols to cope with the punctured clock. the rate 3 / 4 timing is shown below as an example. symckin dclkin for rate 3 / 4 operation it is possible to generate the two clocks with a mutual phase relationship that can exclude the timing violation, as was shown in the first figure. as previously stated, provided the two clocks can be generated as shown in the first example, where only the rising edges of dclkin coincide with the edges of symckin, the timing violation will never occur provided that the delay from the non- coincident rising edges of symckin to the following falling edge of dclkin (shown by the arrows) exceeds 8 nsec. in the example shown this will be true at data rates up to 30 mbps. care must be taken to ensure that jitter between the clocks is kept low enough to avoid the timing violation condition. a similar condition exists for rate 2 / 3 operation, as shown below. symckin dclkin symckin dclkin however, in this case the timing violation will begin to occur at speeds over 15 mbps, so that this method of solving the timing problem is less useful for rate 7 / 8 operation. note that for sequential mode operation (parl = 0) the frequency of the symckin signal will be doubled in every case. this presents a problem with the synchronized clock method presented here since it will not be possible to generate the necessary waveforms with the correct mutual phasing guaranteed because of the phase ambiguity of the symckin signal itself relative to the internal handover process. in this case it will be necessary to use either the punctured clock approach or the synchronized reset approach. the third method, which, while having the disadvantage that it is susceptible to loss of sync from disturbances, is easier to implement than clock puncturing and provides a lot more margin than simple clock phase synchronization. it consists of a synchronized reset generator used in conjunction with clock phase synchronization. this is shown below for rate 7 / 8 . reset symckin dclkin a ??? ?? 15 nsec. min. this ensures that the STEL-2060Cc starts up during the optimum phase of the symckin/dclkin repetition cycle, i.e., the phase with the maximum separation between the rising edge of symckin and the next falling edge of dclkin;
9 STEL-2060C the decoder will then continue to operate correctly provided that nothing occurs to upset this cycle. this method exploits the fact that not all falling edges of dclkin have a timing sensitivity relative to the rising edges of symckin, as was discussed earlier. for example, in rate 7 / 8 operation only every fourth falling edge of dclkin is critical, starting with the fourth one after the reset is released. by timing the rising edge of the reset at a point in the cycle where there is good separation between the rising edge of symckin and the following falling edge of dclkin the same situation will occur again every four cycles of dclkin, which is precisely where the timing sensitivity occurs, as shown in the figure. this method ensures good timing margins for stable operation at all data rates up to 40 mbps, this limit again being set by the symbol setup and hold time requirements and need to use square waves for the clocks. electrical characteristics absolute maximum ratings warning: stresses greater than those shown below may cause permanent damage to the device. exposure of the device to these conditions for extended periods may also affect device reliability. symbol parameter range units t stg storage temperature C65 to +150 c t a operating temperature (ambient) C40 to +85 c v ddmax max. voltage between v dd and v ss +7 to C0.7 volts v i/o(max) max. voltage on any input or output pin v dd + 0.3 volts v i/o(min) min. voltage on any input or output pin v ss C 0.3 volts recommended operating conditions symbol parameter range units v dd supply voltage +5 10% volts t a operating temperature (ambient) 0 to +70 c d.c. characteristics (operating conditions: v dd = 5.0 5% volts, t a = 0 to 70 c) symbol parameter min. typ. max. units conditions i dd(q) supply current, quiescent 1.0 ma static, no clock i dd supply current, operational 8 ma/mbps @ 45 mbps ( f data ) v ih(min) min. high level input voltage 2.0 volts guaranteed logic '1' v il(max) max. low level input voltage 0.8 volts guaranteed logic '0' v oh(min) min. high level output voltage 2.4 volts i o = C4.0 ma v ol(max) max. low level output voltage 0.4 volts i o = +4.0 ma i ih(max) max. high level input current 10 m av in = +5.0 volts i il(max) max. low level input current C10 m av in = 0 volts
STEL-2060C 10 (a) parallel input mode (parl = 1) timing. rate 1 / 2 and external depuncturing (b) sequential input mode (parl = 0) g1/2 g1 g2 g2 dato ldg2 pncg2 g1 g2 g1 g2 g1 odclk symckin pncg1 t su t hd t shs t so t od t sls g1/2 pncg1/g2 symckin symb. n dato odclk symb. n+1 symb. n+2 t shpe t su t hd t so t od t slpe
11 STEL-2060C a.c. characteristics (operating conditions: v dd = 5.0 5% volts, t a = 0 to 70 c) symbol parameter min. max. units conditions f dat data speed, parallel input mode ( parl = 1), 45 mbps parl = 1 and all rates when not using internal depuncturing rate 2-0 = 0 f dat data speed, sequential input mode ( parl = 0), rate 1 / 2 45 mbps parl = 0 or and all rates and modes when using internal depuncturing rate 2-0 1 0 t su g1 , g2 , pncg1 or pcng2 , ldg2 to symckin setup 3 nsecs. parl = 0 or t hd g1 , g2 , pncg1 or pcng2 , ldg2 to symckin hold 5 nsecs. rate 2-0 = 0 t sui g1 , g2 , pncg1 or pcng2 , ldg2 to symckin setup 6 nsecs. parl = 1 and t hdi g1 , g2 , pncg1 or pcng2 , ldg2 to symckin hold 6 nsecs. rate 2-0 1 0 t shpe, t slpe symckin pulse width (high or low), parallel input mode, 10 nsecs. parl = 1 and all rates when not using internal depuncturing rate 2-0 = 0 t shpi, t slpi symckin pulse width (high or low), parallel input mode, 12 nsecs. parl = 1 and all rates when using internal depuncturing rate 2-0 1 0 t shs, t sls symckin pulse width (high or low), serial input mode 6 nsecs. parl = 0 t so symckin to odclk stable delay ( rate 2-0 = 000) 3 8 nsecs. t do dclkin to odclk stable delay ( rate 2-0 1 000) 3 8 nsecs. load = 15 pf t od odclk to output stable delay, all other outputs 1 3 nsecs. load = 15 pf } } } } } }
STEL-2060C 12 punctured symbol sequences 1. rate 1 / 2 and external depuncturing - sequential inputs (parl = 0) rate symbol sequence (suffix is symbol number in sequence, all at g1 2-0 input) symckin dclkin 1 / 2 g1 1 g2 1 g1 2 g2 2 g1 3 g2 3 (not punctured) 2 d 0 2 / 3 g1 1 g2 1 p 2 g2 2 g1 3 g2 3 p 4 g2 4 g1 5 g2 5 p 6 g2 6 2 d 0 3 / 4 g1 1 g2 1 p 2 g2 2 g1 3 p 3 g1 4 g2 4 p 5 g2 5 g1 6 p 6 g1 7 g2 7 2 d 0 4 / 5 g1 1 g2 1 p 2 g2 2 p 3 g2 3 p 4 g2 4 g1 5 g2 5 p 6 p 6 g2 7 p 7 2 d 0 5 / 6 g1 1 g2 1 p 2 g2 2 g1 3 p 3 p 4 g2 4 g1 5 p 5 g1 6 g2 6 p 7 g2 7 2 d 0 6 / 7 g1 1 g2 1 p 2 g2 2 p 3 g2 3 g1 4 p 4 p 5 g2 5 g1 6 p 6 g1 7 g2 7 2 d 0 7 / 8 g1 1 g2 1 p 2 g2 2 p 3 g2 3 p 4 g2 4 g1 5 p 5 p 6 g2 6 g1 7 p 7 2 d 0 2. rate 1 / 2 and external depuncturing - parallel inputs (parl = 1) rate input symbol sequence (suffix is symbol number in sequence) symckin dclkin 1 / 2 g1 2-0 g1 1 g1 2 g1 3 g1 4 g1 5 g1 6 (not punctured) d 0 g2 2-0 g2 1 g2 2 g2 3 g2 4 g2 5 g2 6 2 / 3 g1 2-0 g1 1 p 2 g1 3 p 4 g1 5 p 6 g1 7 p 8 g1 9 p 10 d0 g2 2-0 g2 1 g2 2 g2 3 g2 4 g2 5 g2 6 g2 7 g2 8 g2 9 g2 10 3 / 4 g1 2-0 g1 1 p 2 g1 3 g1 4 p 5 g1 6 g1 7 p 8 g1 9 g1 10 d0 g2 2-0 g2 1 g2 2 p 3 g2 4 g2 5 p 6 g2 7 g2 8 p 9 g2 10 4 / 5 g1 2-0 g1 1 p 2 p 3 p 4 g1 5 p 6 p 7 p 8 g1 9 p 10 d0 g2 2-0 g2 1 g2 2 g2 3 g2 4 g2 5 g2 6 g2 7 g2 8 g2 9 g2 10 5 / 6 g1 2-0 g1 1 p 2 g1 3 p 4 g1 5 g1 6 p 7 g1 8 p 9 g1 10 d0 g2 2-0 g2 1 g2 2 p 3 g2 4 p 5 g2 6 g2 7 p 8 g2 9 p 10 6 / 7 g1 2-0 g1 1 p 2 p 3 g1 4 p 5 g1 6 g1 7 p 8 p 9 g1 10 d0 g2 2-0 g2 1 g2 2 g2 3 p 4 g2 5 p 6 g1 7 g2 8 p 9 g2 10 7 / 8 g1 2-0 g1 1 p 2 p 3 p 4 g1 5 p 6 g1 7 g1 8 p 9 p 10 d0 g2 2-0 g2 1 g2 2 g2 3 g2 4 p 5 g2 6 p 7 g2 8 g2 9 g2 10 3. internal depuncturing - sequential inputs (parl = 0) rate symbol sequence (suffix is symbol number in sequence, all at g1 2-0 input) symckin dclkin 1 / 2 g1 1 g2 1 g1 2 g2 2 g1 3 g2 3 g1 4 g2 4 g1 5 (not punctured) 2 d 0 2 / 3 g1 1 g2 1 g2 2 g1 3 g2 3 g2 4 g1 5 g2 5 g2 6 g1 7 g2 7 g2 8 3 / 2 dd 3 / 4 g1 1 g2 1 g2 2 g1 3 g1 4 g2 4 g2 5 g1 6 g1 7 g2 7 g2 8 g1 9 4 / 3 dd 7 / 8 g1 1 g2 1 g2 2 g2 3 g2 4 g1 5 g2 6 g1 7 g1 8 g2 8 g2 9 g2 10 8 / 7 dd 4. internal depuncturing - parallel inputs (parl = 1) rate input symbol sequence (suffix is symbol number in sequence) symckin dclkin 1 / 2 g1 2-0 g1 1 g1 2 g1 3 g1 4 g1 5 g1 6 g1 7 (not punctured) d 0 g2 2-0 g2 1 g2 2 g2 3 g2 4 g2 5 g2 6 g2 7 2 / 3 g1 2-0 g1 1 g2 2 g2 3 g1 5 g2 6 g2 7 g1 9 g2 10 g2 11 3 / 4 dd g2 2-0 g2 1 g1 3 g2 4 g2 5 g1 7 g2 8 g2 9 g1 11 g2 12 3 / 4 g1 2-0 g1 1 g2 2 g1 4 g2 5 g1 7 g2 8 g1 10 g2 11 g1 13 g2 14 2 / 3 dd g2 2-0 g2 1 g1 3 g2 4 g1 6 g2 7 g1 9 g2 10 g1 12 g2 13 g1 15 7 / 8 g1 2-0 g1 1 g2 2 g2 4 g2 6 g1 8 g2 9 g2 11 g1 13 g1 15 g2 16 4 / 7 dd g2 2-0 g2 1 g2 3 g1 5 g1 7 g2 8 g2 10 g1 12 g2 14 g2 15 g1 17
13 STEL-2060C g1 n g1 dato dclkin odclk symckin * g2 n+1 ** g2 n+2 g2 n g2 g1 n+2 g2 n+3 *** g1 n+4 g2 n+4 ** g1 n+1 punctured *** g1 n+3 punctured basic pattern t do t od t sui t hdi * within each symbol period, rising edge of symclkin must precede falling edge, as shown t shpi t slpi (a) parallel input mode (parl = 1) internal depuncturing timing. rate 2 / 3 shown (b) sequential input mode (parl = 0) t od g1/2 g1 n g2 n g2 n+4 g2 n+1 ** g1 n+2 g2 n+2 g2 n+3 *** g1 n+4 symckin dato dclkin odclk ** g1 n+1 punctured *** g1 n+3 punctured basic pattern t do t sui t hdi t shs t sls
STEL-2060C 14 g1/2 g2 g1 g2 g1 g2 g1 g2 g1 g2 g1 g2 g1 g2 g1 g2 pncg1 pncg2 ***** symckin dato odclk ldg2 t su t hd * indicates punctured symbols (a) parallel input mode (parl = 1) external depuncturing timing. rate 3 / 4 shown g1 g2 pncg1 pncg2 *** ** symckin dato odclk * indicates punctured symbols t su t hd (b) sequential input mode (parl = 0)
15 STEL-2060C addr 2-0 data 7-0 write csel don't care don't care addr 2-0 read csel data 7-0 don't care don't care t sm t hm t ww t hm t sm t zv t vz 1. write mode 2. read mode a.c. characteristics (operating conditions: v dd = 5.0 5% volts, t a = 0 to 70 c) symbol parameter min. max. units t sm csel , addr 2-0 or data 7-0 to write or read setup 10 nsecs. t hm csel , addr 2-0 or data 7-0 to write or read hold 5 nsecs. t ww write pulse width 5 nsecs. t zv read (low) to data 7-0 valid 10 nsecs. t vz read (high) to data 7-0 high-impedance 10 nsecs. microprocessor interface timing
STEL-2060C 16 node synchronization in a communication system using viterbi decoding the de- coder will only operate correctly when the symbols g1 and g2 are loaded into the decoder in the correct order. identi- fying which symbol is g1 and which one is g2 is referred to as node synchronization. the STEL-2060C contains a circuit designed to carry out the node synchronization function automatically. it uses the internally generated metrics of the received sequence to do this. these constantly changing parameters are periodically renormalized to keep them within bounds. if renormalization occurs too frequently it is a good indication that the system is not converging, most likely due to lack of node synchronization. the renormal- ization rate at which the system will decide to change the node sync is determined by the threshold parameter. this is an 8-bit number which is set by the thr 7-0 inputs. when the renormalization count exceeds this value, the oos output will go high and the auto output will pulse high for one clock cycle, as shown during count window n in the timing diagram below. the counter is reset after a number of bits determined by the number set by the count 7-0 inputs, so that the threshold must be exceeded somewhere in that period for resynchronization to take place. oos will be reset if the counter then counts through an entire window and the threshold is not exceeded, as shown during count window n + 1 in the timing diagram below. the most suitable threshold setting will depend on the value of e b /n 0 , the coding rate, and the signal level at the g1 and g2 inputs. for full scale inputs, i.e., the peak signal values almost saturate the digital inputs, suitable starting values for the threshold will be 1% for rate 1 / 2 , 0.5% for rates 2 / 3 to 6 / 7 , and 0.1% for rate 7 / 8 . e.g., for rate 1 / 2 , if the number of bits over which the measure is made is set to 512 ( count 7-0 = 01 h ) the threshold should be set to 5. setting thr 7-0 = 0 gives a value of 6, which is adequately close. more reliable results will be obtained by counting over a longer period to improve the averaging process, but this increases the time taken to make a decision and hence to acquire node sync. thus, starting with a low count period and then increasing it (and adjusting the threshold accord- ingly to maintain a value of 1%) when oos goes low will result in a faster acquisition of correct node sync with a lower probability of accidental loss of node sync once cor- rect sync has been achieved. to use the internal node sync the auto output must be connected to the sync input. the synchronization sequence depends on the setting of the parl input. when parl is set low it is assumed that the data was modulated using bpsk, and when it is set high it is assumed that the data was modulated using qpsk. the appropriate synchronization sequences will be invoked, as shown in the node sync sequence tables. note that the pipeline delay through the device will be affected by the node sync state. if multiple devices are used in parallel to achieve higher data rates, it is necessary for the all devices to have the same node sync state to equalize their pipeline delays. it will be necessary to reset the devices together to achieve this state when internal depuncturing is used, additional node sync states exist because of the uncertainty of the current symbol position in the puncture sequence. in this case the node sync circuit will also search through the sequence by adding delays in the depuncturing process to precess through the sequence. in the sequential input mode ( parl = 0) this is simply an extension of the node sync process, since the alternate state is achieved by delaying the symbols. in the parallel input mode, however, this is different from the "invert g2 and swap" process, and in this sync sequence "invert g2 and swap" precedes the delay addition, so that the system goes through both the initial and alternate states for each delay addition tried. this is shown for the rate 2 / 3 case. in each case the symbols are read into the depunc- turing circuit in groups of three (in the bpsk mode) or six (in the qpsk mode) and attempts are made to reinsert the punctured symbol in all of the possible insertion positions. the positions of the punctured symbols in the sequences are shown by the asterisks (*). the resulting groups of four or eight symbols are then decoded in pairs, resulting in two decoded bits in the bpsk mode and four bits in the qpsk mode. for higher rates the sequences will be extensions of this procedure. when external depuncturing is used, the determination of which symbols were punctured, and need to be reinserted into the symbol sequence, is part of the node sync process. this is because the acquisition of correct node sync cannot be completed until the punctured symbols are reinserted cor- rectly. the auto and oos outputs of the STEL-2060C can be used as indicators of the operation of the internal node sync process; oos will remain high as long as node sync has not been achieved and auto will pulse each time a new node sync state is being tried. since there are only two possible internal node sync states, alternate pulses on the auto output can be used as an indication that the depunc- turing is incorrect and a new depuncturing sequence should be tried externally. node sync timing auto oos odclk count window n count window n+1
17 STEL-2060C input initial state alternate states 12 g1 g1 n g2 n *g2 n+1 g2 n *g2 n+1 g1 n+2 g2 n+1 g1 n+2 g2 n+2 * (no delay) (one symbol (two symbol delay) delay) parl input initial state alternate state 0g1g1 n g2 n g2 n g1 n+1 g2 n.a. n.a. 1g1g1 n g2 n g2 g2 n g1 n input initial state alternate states 12345 g1 g1 n g2 n+1 g2 n+2 *g2 n *g1 n+2 g2 n+3 g2 n *g1 n+2 g2 n+3 g2 n+1 g2 n+2 *g1 n+4 *g2 n+1 g2 n+2 *g1 n+4 g1 n+2 g2 n+3 g2 n+4 * g2 g2 n *g1 n+2 g2 n+3 g1 n g2 n+1 g2 n+2 *g2 n+1 g2 n+2 *g1 n+4 g2 n *g1 n+2 g2 n+3 g1 n+2 g2 n+3 g2 n+4 g2 n+1 g2 n+2 *g1 n+4 (no invert/swap (invert/swap (no invert/swap (invert/swap (no invert/swap (invert/swap no delay) no delay) one symb. delay) one symb. delay) two symb. delay) two symb. delay) 3. rate 2 / 3 , parl = 1 (qpsk mode) node sync sequences 1. rate 1 / 2 2. rate 2 / 3 , parl = 0 (bpsk mode) ber performance the coding gain obtained by the use of convolutional coding and viterbi decoding is extremely dependent on many parameters. not surprisingly, the code rate is a primary factor, but so are the bit error rate (ber) and amplitude of the input signal. the ber affects the coding gain because the error correction capability of the viterbi decoder is dependent on the statistics of the errors, specifically the clustering of errors. as the ber of the input signal increases, so does the clustering, causing a reduction in the error correcting capability of the device, along with the coding gain. the signal amplitude is important because of the weighting given to the signal amplitude as an indication of the likelihood of an error in a given symbol pair. e b /n o ber 10 C2 10 C3 10 C4 10 C5 10 C6 10 C7 r = 1 / 2 r = 2 / 3 r = 3 / 4 r = 7 / 8 10 9 8 7 6 5 4 3 2 uncoded 10 C1 11 consequently it is important to maintain the signal amplitude at an optimum level in order to maximize the performance. the performance curves shown above were measured using a digital link simulator with the signal level set at one half of full scale; i.e., the signal amplitude without noise ranged from 101 to 001 in signed magnitude format, or 101 to 010 in offset binary format. the coding gain under these conditions is about 0.2 db less than that under optimum signal level conditions. the performance of the STEL-2060C is shown here for unpunctured operation (rate 1 / 2 ) as well as punctured operation at the rates for which internal depuncturing is supported (rates 2 / 3 , 3 / 4 and 7 / 8 ). the error rate for uncoded data is shown for comparison.
STEL-2060C 18 qpsk communication system using convolutional encoding and viterbi decoding. rate = 1 / 2 application information the STEL-2060C can be used in a variety of different environments. one example of a system using a convolutional encoder with the STEL-2060C viterbi decoder is illustrated here. the STEL-2060C cannot be used as a common decoder in multi-channel applications because of the memory incorporated on the chip which is dedicated to a single channel. the system modulates a data stream of rate 45 mbps using binary psk (bpsk) or quaternary psk (qpsk). to be able to use convolutional coding, the system must either have available the additional bandwidth needed to transmit symbols at a higher rate or must be able to make use of higher levels of modulation. e.g., by changing from bpsk to qpsk modulation, the data can be encoded at rate 1 / 2 without requiring any additional bandwidth. the performance improvement that can be expected is shown in the graph below. the STEL-2060C is designed to accept symbols synchronously. symckin is supplied by the user to clock in the symbols. the maximum data rate is 45 mbps, using a symckin frequency of 45 mhz (when parl is set high) or 90 mhz (when parl is set low) at rate 1 / 2 , corresponding to 90 msymbols per sec. rate 1/2 conv. encoder qpsk demod. rate 1/2 viterbi decoder qpsk modulator channel bw=90 mhz coded data @ 90 mbps tx data 45 mbps rx data 45 mbps coded data @ 90 mbps i q i q 2345678910 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 12 3 2 6 3 2 6 3 2 6 3 2 6 3 2 6 3 2 6 10 ? 11 e b /n 0 db ber uncoded coding gain coded

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